FIG. 1 shows an example of typical architecture for a server or a PC station arrangement 100 with a processor 110 having four (4) cores (Core1-Core4). Internal to the processor, each core has its dedicated caches (Core1-L1-Core4-L1, Core1-L2-Core4-L2) and a shared cache (L3, in this example). All these internal memory elements are typically based on (e.g.) SRAM technology. SRAM offers very low latencies, very high speed and unlimited endurance. However, this implementation is costly, offers limited capacity, and is volatile (loses data in case of a power loss).
Away from the processor 100, dynamic random access memory (DRAM) 120 is currently the fastest acting memory that is accessible. DRAM components are available in various form factors: dual-inline memory module (DIMM), non-volatile DIMM (NVDIMM), or other customized memory arrangements, which should be clear to those of skill. In the exemplary computing arrangement 100 shown in FIG. 1, the processor 110 accesses the DRAM components through the dual data rate (DDR) interface 122, including a conventional North Bridge 124. DRAM is very area-efficient compared to static RAM (SRAM), and hence provides relatively higher capacity at lower unit cost, compared to SRAM. DRAM also offers low latencies, high speeds, high endurance, and is relatively lower cost than SRAM. However, DRAM is still costly when compared to other storage media, and is volatile.
Beyond DRAM, various storage memory technologies, such as Flash, magnetic, and/or optical storage are available for large scale non-volatile data storage, referred to generally as “traditional mass storage” 140. Traditional mass storage capacities can run into terabyte (TB), petabyte (PB) and beyond. The processor accesses the traditional mass storage devices through the I/O interconnect 130 and associated South Bridge 132 shown in FIG. 1. Note that I/O interconnect further provides several bus-based interface architectures 150, such as Gen-Z, Ethernet, SATA, PCIe, SAS, SCSI, iSCSI, etc. to reach the individual mass storage devices 142, 144, 146, 148 and 149. Traditional mass storage” devices offer high capacities of non-volatile memory at relatively very lower cost per gigabyte (GB). However, such mass storage arrangements have high latency, slower speeds and limited endurance.
New digital electronic memory implementations broadly referred to as “Storage Class Memories” are designed to fall between DRAM and Mass Storage memories in almost all metrics. These include emerging technologies like Resistive RAM (ReRAM), Phase Change Memories (PCM) among others. In addition to the topology shown and described in FIG. 1 for the Memory Bus (122) and I/O interconnect (130), additional exemplary topologies are provided in the computer arrangements 200 and 300 of FIGS. 2 and 3, respectively. As described above, in the arrangement 100 of FIG. 1, the memory bus (using Double Data Rate Protocol, DDR) 120 and I/O interconnect 130 are each instantiated in discrete chipsets/dies, associated with the North Bridge 124 and South Bridge 132, respectively.
Thus, in the exemplary arrangement 200 of FIG. 2, the memory bus 222 originates directly from the processor 210, while I/O interconnect 230 (connected to the mass storage 240 using bus architectures 250) originates in an external I/O chipset 234. Associated I/O connections 212 and 214 respectively connect and control the I/O chipset 234 and memory bus 222, and are provided on the die of the processor 210 in this example. The memory bus 222 accesses DRAM (DIMM and NVDIMM) 220 in a conventional manner.
In the exemplary arrangement 300 of FIG. 3, all the interfaces (I/O interconnect 330, SAS 352, Ethernet 354, SATA 356, PCIe 358, others 359, and memory controller 314) are instantiated directly within the die of the processor 310. These communicate via appropriate data bus architectures with traditional mass data storage 340 of various types, as described above. As described above, according to a conventional implementation, the exemplary processor arrangement 310 accesses DRAM (DIMM, NVDIMM) 320 through the memory bus 322. Other exemplary topologies using Gen-Z and/or similar emerging technologies are also available as a combination of ones shown in FIG. 1, FIG. 2 and/or FIG. 3.
Some NVDIMM implementations (NVDIMM-N) have DRAM and Flash memory, arranged so that Flash has just enough space to accommodate the content stored in DRAM. For example, an NVDIMM with 8 GB DRAM may have 8 GB to 16 GB of Flash memory associated therewith. In case of power loss or another failure condition, data from DRAM is backed up in the Flash memory, thereby providing a failover solution. When power is restored, the data is restored from the flash memory to the DRAM, and processing continues as before. In this implementation, as shown in the exemplary arrangement 400 of FIG. 4, only DRAM 424 of the DIMM/NVDIMM module 420 is directly addressable on the memory bus 422 and flash memory 426 is not directly addressable on the memory bus 422. A controller 428, and associated function, manages interaction between DRAM 424 and flash 426, and more particularly facilitates moving data from the volatile DRAM to Flash memory and vice versa. Thus, even though there are two types of memories instantiated on the DIMM/NVDIMM module, there is effectively only one layer of addressable memory.
In other NVDIMM implementations (NVDIMM-F), DRAM is used as an internal buffer and is not addressable on memory bus by the processor arrangement 410, etc. Instead, the flash memory is directly addressable on the memory bus. Just like in NVDIMM-N, even though there are two types of memories on the NVDIMM, there is only one layer of addressable memory. Note that in each of the above implementations, NVDIMMs offer limited capacity, due to the limitation on available real estate on the DIMM modules. Likewise, in the depicted arrangements, the only way data can be moved from processor to NVDIMM and vice versa, without (free of) physically disconnecting the persistent storage elements (e.g. Flash 426, mass storage 525) and re-attaching them to the I/O bus 430 directly, is through the memory bus (i.e. DDR interface). This incurs heavy processing penalty for data movement in and out of NVDIMMs. Since NVDIMM data is not available on the I/O interconnect (430 in FIG. 4) and associated mass storage 440 (via buss architectures 450), NVDIMMs cannot be the final resting place for data in this example.
Each of the above-described arrangements essentially separates I/O linking mass storage and I/O linking DRAM into two separate channels, each of which required its own addressing and communication protocols and functions. DRAM is accessed for working data memory used in relatively contemporaneous processes, and the size of this data space is relatively limited; while mass storage is accessed for large data files and to store processing results for subsequent retrieval at an indefinite future time, and its size can be virtually unlimited.